3D TCAD Study of the Implications of Channel Width and Interface States on FD-SOI Z2-FETs
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AuteurNavarro Moral, Carlos; Navarro Moral, Santiago; Márquez González, Carlos; Padilla De la Torre, José Luis; Galy, Philippe; Gámiz Pérez, Francisco Jesús
1T-DRAMZ2-FETSemiconductor memoriesSilicon on insulatorCapacitorlessFully depleted (FD)
PatrocinadorH2020 REMINDER European (grant agreement No 687931) and Spanish National TEC2017-89800-R and PCIN-2015-146 projects are acknowledged for financial support.
3-D numerical technology computer-aided design simulations, based on experimental results, are performed to study the origin of the large Z 2 -FET dynamic random access memory (DRAM) memory cell-to-cell variability on fully depleted silicon-on-insulator (FD-SOI) technology. The body width, cross section shape, and the passivation-induced lateral and top interface state density impacts on the device dynamic memory operation are investigated. The width and body shape arise as marginal metrics not strongly inducing fluctuations in the device triggering conditions. However, the interface state (D it ) control, especially at the top of the ungated section, emerges as the main challenge since traps significantly increase the ON-voltage variability threatening the capacitor-less DRAM operation.