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dc.contributor.authorNavarro Moral, Carlos 
dc.contributor.authorNavarro Moral, Santiago
dc.contributor.authorMárquez González, Carlos 
dc.contributor.authorPadilla De la Torre, José Luis 
dc.contributor.authorGaly, Philippe
dc.contributor.authorGámiz Pérez, Francisco Jesús
dc.description.abstract3-D numerical technology computer-aided design simulations, based on experimental results, are performed to study the origin of the large Z 2 -FET dynamic random access memory (DRAM) memory cell-to-cell variability on fully depleted silicon-on-insulator (FD-SOI) technology. The body width, cross section shape, and the passivation-induced lateral and top interface state density impacts on the device dynamic memory operation are investigated. The width and body shape arise as marginal metrics not strongly inducing fluctuations in the device triggering conditions. However, the interface state (D it ) control, especially at the top of the ungated section, emerges as the main challenge since traps significantly increase the ON-voltage variability threatening the capacitor-less DRAM operation.es_ES
dc.description.sponsorshipH2020 REMINDER European (grant agreement No 687931) and Spanish National TEC2017-89800-R and PCIN-2015-146 projects are acknowledged for financial support.es_ES
dc.relationGrant agreement No 687931es_ES
dc.rightsCreative Commons Attribution-NonCommercial-NoDerivs 3.0 License
dc.subjectSemiconductor memorieses_ES
dc.subjectSilicon on insulatores_ES
dc.subjectFully depleted (FD)es_ES
dc.title3D TCAD Study of the Implications of Channel Width and Interface States on FD-SOI Z2-FETses_ES

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Creative Commons Attribution-NonCommercial-NoDerivs 3.0 License
Except where otherwise noted, this item's license is described as Creative Commons Attribution-NonCommercial-NoDerivs 3.0 License