@misc{10481/57447, year = {2019}, month = {5}, url = {http://hdl.handle.net/10481/57447}, abstract = {3-D numerical technology computer-aided design simulations, based on experimental results, are performed to study the origin of the large Z 2 -FET dynamic random access memory (DRAM) memory cell-to-cell variability on fully depleted silicon-on-insulator (FD-SOI) technology. The body width, cross section shape, and the passivation-induced lateral and top interface state density impacts on the device dynamic memory operation are investigated. The width and body shape arise as marginal metrics not strongly inducing fluctuations in the device triggering conditions. However, the interface state (D it ) control, especially at the top of the ungated section, emerges as the main challenge since traps significantly increase the ON-voltage variability threatening the capacitor-less DRAM operation.}, organization = {H2020 REMINDER European (grant agreement No 687931) and Spanish National TEC2017-89800-R and PCIN-2015-146 projects are acknowledged for financial support.}, keywords = {1T-DRAM}, keywords = {Z2-FET}, keywords = {Semiconductor memories}, keywords = {Silicon on insulator}, keywords = {Capacitorless}, keywords = {Fully depleted (FD)}, title = {3D TCAD Study of the Implications of Channel Width and Interface States on FD-SOI Z2-FETs}, doi = {10.1109/TED.2019.2912457}, author = {Navarro Moral, Carlos and Navarro Moral, Santiago and Márquez González, Carlos and Padilla De la Torre, José Luis and Galy, Philippe and Gámiz Pérez, Francisco Jesús}, }