3D TCAD Study of the Implications of Channel Width and Interface States on FD-SOI Z2-FETs Navarro Moral, Carlos Navarro Moral, Santiago Márquez González, Carlos Padilla De la Torre, José Luis Galy, Philippe Gámiz Pérez, Francisco Jesús 1T-DRAM Z2-FET Semiconductor memories Silicon on insulator Capacitorless Fully depleted (FD) 3-D numerical technology computer-aided design simulations, based on experimental results, are performed to study the origin of the large Z 2 -FET dynamic random access memory (DRAM) memory cell-to-cell variability on fully depleted silicon-on-insulator (FD-SOI) technology. The body width, cross section shape, and the passivation-induced lateral and top interface state density impacts on the device dynamic memory operation are investigated. The width and body shape arise as marginal metrics not strongly inducing fluctuations in the device triggering conditions. However, the interface state (D it ) control, especially at the top of the ungated section, emerges as the main challenge since traps significantly increase the ON-voltage variability threatening the capacitor-less DRAM operation. 2019-10-21T08:38:16Z 2019-10-21T08:38:16Z 2019-05-06 info:eu-repo/semantics/article http://hdl.handle.net/10481/57447 10.1109/TED.2019.2912457 eng Grant agreement No 687931 http://creativecommons.org/licenses/by-nc-nd/3.0/ info:eu-repo/semantics/openAccess Creative Commons Attribution-NonCommercial-NoDerivs 3.0 License