Z2-FET as Capacitor-Less eDRAM Cell For High-Density Integration
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AuthorNavarro Moral, Carlos; Duan, Meng; Parihar, Mukta Singh; Adamu-Lema, Fikru; Coseman, Stefan; Lacord, Joris; Lee, Kyunghwa; Sampedro Matarín, Carlos; Cheng, Binjie; El Dirani, Hassam; Barbe, Jean-Charles; Fonteneau, Pascal; Kim, Seong; Cristoloveanu, Sorin; Bawedin, Maryline; Millar, Campbell; Galy, Philippe; Le Royer, Cyrille; Karg, Sigfried; Riel, Heike; Wells, Paul; Kim, Yong Tae; Asenov, Asen; Gámiz Pérez, Francisco Jesús
1T-DRAMZ2-FETCapacitorlessFully depleted (FD)
Sponsorship2016 REMINDER project (grant agreement No 687931) is thanked for financial support
2-D numerical simulations are used to demonstrate the Z2-FET as a competitive embedded capacitorless dynamic random access memory cell for low-power applications. Experimental results in 28-nm fully depleted silicon on insulator technology are used to validate the simulations prior to downscaling tests. Default scaling, without any structure optimization, and enhanced scaling scenarios are considered before comparing the bit cell area consumption and integration density with other eDRAM cells in the literature.