Z2-FET as Capacitor-Less eDRAM Cell For High-Density Integration Navarro Moral, Carlos Duan, Meng Parihar, Mukta Singh Adamu-Lema, Fikru Coseman, Stefan Lacord, Joris Lee, Kyunghwa Sampedro Matarín, Carlos Cheng, Binjie El Dirani, Hassam Barbe, Jean-Charles Fonteneau, Pascal Kim, Seong Cristoloveanu, Sorin Bawedin, Maryline Millar, Campbell Galy, Philippe Le Royer, Cyrille Karg, Sigfried Riel, Heike Wells, Paul Kim, Yong Tae Asenov, Asen Gámiz Pérez, Francisco Jesús 1T-DRAM Z2-FET Capacitorless Fully depleted (FD) 2-D numerical simulations are used to demonstrate the Z2-FET as a competitive embedded capacitorless dynamic random access memory cell for low-power applications. Experimental results in 28-nm fully depleted silicon on insulator technology are used to validate the simulations prior to downscaling tests. Default scaling, without any structure optimization, and enhanced scaling scenarios are considered before comparing the bit cell area consumption and integration density with other eDRAM cells in the literature. 2019-10-21T07:53:14Z 2019-10-21T07:53:14Z 2017-10-31 journal article http://hdl.handle.net/10481/57442 10.1109/TED.2017.2759308 eng http://creativecommons.org/licenses/by-nc-nd/3.0/ open access Creative Commons Attribution-NonCommercial-NoDerivs 3.0 License