@misc{10481/57442,
year = {2017},
month = {10},
url = {http://hdl.handle.net/10481/57442},
abstract = {2-D numerical simulations are used to demonstrate the Z2-FET as a competitive embedded capacitorless dynamic random access memory cell for low-power applications. Experimental results in 28-nm fully depleted silicon on insulator technology are used to validate the simulations prior to downscaling tests. Default scaling, without any structure optimization, and enhanced scaling
scenarios are considered before comparing the bit cell area consumption and integration density with other eDRAM
cells in the literature.},
organization = {2016 REMINDER project (grant  agreement  No  687931)  is thanked for financial support},
keywords = {1T-DRAM},
keywords = {Z2-FET},
keywords = {Capacitorless},
keywords = {Fully depleted (FD)},
title = {Z2-FET as Capacitor-Less eDRAM Cell For High-Density Integration},
doi = {10.1109/TED.2017.2759308},
author = {Navarro Moral, Carlos and Duan, Meng and Parihar, Mukta Singh and Adamu-Lema, Fikru and Coseman, Stefan and Lacord, Joris and Lee, Kyunghwa and Sampedro Matarín, Carlos and Cheng, Binjie and El Dirani, Hassam and Barbe, Jean-Charles and Fonteneau, Pascal and Kim, Seong and Cristoloveanu, Sorin and Bawedin, Maryline and Millar, Campbell and Galy, Philippe and Le Royer, Cyrille and Karg, Sigfried and Riel, Heike and Wells, Paul and Kim, Yong Tae and Asenov, Asen and Gámiz Pérez, Francisco Jesús},
}