Capacitor-less dynamic random access memory based on a III–V transistor with a gate length of 14 nm
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AuteurNavarro Moral, Carlos; Karg, Sigfried; Márquez González, Carlos; Navarro Moral, Santiago; Convertino, Clarissa; Zota, Cezar; Czornomaz, Lukas; Gámiz Pérez, Francisco Jesús
1T-DRAMIII-VIndium Galium ArsenideMSDRAMCapacitorlessFully depleted (FD)MSDRAM
PatrocinadorH2020 REMINDER European (grant agreement No 687931) and TEC2014-59730 and P12-TIC-1996 National projects are thanked for financial support
Dynamic random access memory (DRAM) cells are commonly used in electronic devices and are formed from a single transistor and capacitor. Alternative approaches, which are based on the floating body effect, have been proposed that could reduce manufacturing complexity and minimize the cell footprint by removing the external capacitor. Such capacitor-less DRAM has been demonstrated in silicon, but the use of other materials, including III–V compound semiconductors, remains relatively unexplored, despite the fact that they could lead to enhanced performance. Here we report capacitor-less one-transistor DRAM cells based on indium gallium arsenide (InGaAs). With our InGaAs on insulator transistors, we demonstrate different current levels for each logic state, and thus successful memory behaviour, down to a gate length of 14 nm.