Design Time Optimization for Hardware Watermarking Protection of HDL Designs
Metadatos
Mostrar el registro completo del ítemAutor
Castillo, E.; Morales Santos, Diego Pedro; García, A.; Parrilla, L.; Todorovich, E.; Meyer Baese, UweEditorial
Wiley
Fecha
2015-03-15Referencia bibliográfica
Castillo, E., Morales, D. P., García, A., Parrilla, L., Todorovich, E., Meyer-Baese, U., Design Time Optimization for Hardware Watermarking Protection of HDL Designs, The Scientific World Journal, 2015, 752969, 14 pages, 2015. https://doi.org/10.1155/2015/752969
Patrocinador
CEI BIOTIC Granada 2014 under Project mP TIC 3, “Compromiso con la investigaciión y el desarrollo.”; Altera Corp.; Xilinx Inc.Resumen
HDL-level design offers important advantages for the application of watermarking to IP cores, but its complexity also requires tools
automating these watermarking algorithms. A new tool for signature distribution through combinational logic is proposed in this
work. IPP@HDL, a previously proposed high-level watermarking technique, has been employed for evaluating the tool. IPP@HDL
relies on spreading the bits of a digital signature at the HDL design level using combinational logic included within the original
system.The development of this new tool for the signature distribution has not only extended and eased the applicability of this
IPP technique, but it has also improved the signature hosting process itself. Three algorithms were studied in order to develop this
automated tool. The selection of a cost function determines the best hosting solutions in terms of area and performance penalties
on the IP core to protect. An 1D-DWT core andMD5 and SHA1 digital signatures were used in order to illustrate the benefits of the
new tool and its optimization related to the extraction logic resources. Among the proposed algorithms, the alternative based on
simulated annealing reduces the additional resources while maintaining an acceptable computation time and also saving designer
effort and time.