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Rule-Based Design for Low-Cost Double-Node Upset Tolerant Self-Recoverable D-Latch
dc.contributor.author | Hatefinasab, Seyedehsomayeh | |
dc.contributor.author | Morales Santos, Diego Pedro | |
dc.contributor.author | Castillo Morales, María Encarnación | |
dc.contributor.author | Rodríguez Santiago, Noel | |
dc.date.accessioned | 2023-02-10T11:55:15Z | |
dc.date.available | 2023-02-10T11:55:15Z | |
dc.date.issued | 2023-01-03 | |
dc.identifier.citation | S. Hatefinasab... [et al.]. "Rule-Based Design for Low-Cost Double-Node Upset Tolerant Self-Recoverable D-Latch," in IEEE Access, vol. 11, pp. 1732-1741, 2023, doi: [10.1109/ACCESS.2022.3233812] | es_ES |
dc.identifier.uri | https://hdl.handle.net/10481/79822 | |
dc.description.abstract | This paper presents a low-cost, self-recoverable, double-node upset tolerant latch aiming at nourishing the lack of these devices in the state of the art, especially featuring self-recoverability while maintaining a low-cost pro le. Thus, this D-latch may be useful for high reliability and high-performance safety-critical applications as it can detect and recover faults happening during holding time in harsh radiation environments. The proposed D-latch design is based on a low-cost single event double-node upset tolerant latch and a rule-based double-node upset (DNU) tolerant latch which provides it with the self-recoverability against DNU, but paired with a low transistor count and high performance. Simulation waveforms support the achievements and demonstrate that this new D-latch is fully self-recoverable against double-node upset. In addition, the minimum improvement of the delay-power-area product of the proposed rule-based design for the low-cost DNU tolerant self-recoverable latch (RB-LDNUR) is 59%, compared with the latest DNU self-recoverable latch on the literature. | es_ES |
dc.description.sponsorship | Spanish Government MCIN/AEI/10.13039/501100011033/FEDER PID2020-117344RB-I00 | es_ES |
dc.description.sponsorship | Regional Government P20_00265 P20_00633 B-RNM-680-UGR20 | es_ES |
dc.language.iso | eng | es_ES |
dc.publisher | IEEE | es_ES |
dc.rights | Atribución 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by/4.0/ | * |
dc.subject | Delay-power-area product (DPAP) | es_ES |
dc.subject | Double node upsets (DNU) | es_ES |
dc.subject | High impedance state (HIS) | es_ES |
dc.subject | Low cost single event double node upset tolerant (LSEDUT) | es_ES |
dc.subject | Power-delay product (PDP) | es_ES |
dc.subject | Single node upset (SNU) | es_ES |
dc.subject | Soft error (SE) | es_ES |
dc.title | Rule-Based Design for Low-Cost Double-Node Upset Tolerant Self-Recoverable D-Latch | es_ES |
dc.type | journal article | es_ES |
dc.rights.accessRights | open access | es_ES |
dc.identifier.doi | 10.1109/ACCESS.2022.3233812 | |
dc.type.hasVersion | VoR | es_ES |