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dc.contributor.authorGonzález Marín, Enrique 
dc.contributor.authorGarcía Ruiz, Francisco Javier 
dc.contributor.authorTienda-Luna, Isabel María
dc.contributor.authorGodoy Medina, Andrés 
dc.contributor.authorGámiz Pérez, Francisco Jesús 
dc.date.accessioned2014-09-08T09:37:22Z
dc.date.available2014-09-08T09:37:22Z
dc.date.issued2012-05
dc.identifier.citationGonzález-Marín, E.; et al. Study of the Gate Capacitance of GaAs, InAs and InGaAs Nanowires. In: 36 th Workshop on Compound Semiconductor Devices and Integrated Circuits (WOCSDICE 2012). Island of Porquerolles (France), 28-30 may 2012. [http://hdl.handle.net/10481/32936]es_ES
dc.identifier.urihttp://hdl.handle.net/10481/32936
dc.description.abstractIn this work, a simulation-based study of the gate capacitance of III-V nanowires is performed by using a 2D Schrödinger-Poisson solver. The effective mass approximation, including non-parabolic corrections, is used to model the semiconductor conduction band. Also,wave-function penetration into the gate dielectric is considered. We assess the impact of parameters such as the gate-insulator effective mass and the satellite conduction band valleys energy offsets.es_ES
dc.description.sponsorshipWork supported by the projects P09-TIC-4873, FIS-2008-05805 and FIS-2011-26005. E. González Marín also acknowledges the FPU program.es_ES
dc.language.isoenges_ES
dc.subjectIII-V compound semiconductorses_ES
dc.subjectNon-parabolic relationshipes_ES
dc.subjectNanowirees_ES
dc.subjectDensity of stateses_ES
dc.subjectGate capacitancees_ES
dc.titleStudy of the Gate Capacitance of GaAs, InAs and InGaAs Nanowireses_ES
dc.typeinfo:eu-repo/semantics/conferenceObjectes_ES
dc.rights.accessRightsinfo:eu-repo/semantics/openAccesses_ES


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