Dual-Doped Reconfigurable FETs for Hardware Security: A TCAD Approach

Abstract

A novel variant of reconfigurable FETs (RFETs), employing source and drain doped terminals instead of Schottky contacts, is explored through TCAD simulations for implementing logic circuits that integrate Design-for-Trust (DfTr) techniques. These include security strategies such as circuit camouflaging and advanced logic locking. Polymorphic Logic Gates (PLGs) based on dual-doped RFET (DD-RFET) technology are designed and validated through mixed-mode simulations at both gate and circuit levels. To demonstrate practical applicability, camouflaging and an URSAT logic-locking scheme are implemented on a small benchmark circuit, and security is evaluated using custom brute-force and SAT-like attacks. While the limited circuit size allows efficient key recovery, results show non-trivial attack effort and significant output corruption for incorrect keys. In addition, DD-RFETs provide enhanced reconfigurability and potentially reduced transistor count compared to conventional CMOS implementations, making them suitable as complementary building blocks for Design-for-Trust applications and as a platform to explore security-oriented circuit design.