@misc{10481/110610,
year = {2026},
month = {1},
url = {https://hdl.handle.net/10481/110610},
abstract = {A novel variant of reconfigurable FETs (RFETs), employing source and drain doped terminals instead of Schottky contacts, is explored through TCAD simulations for implementing logic circuits that integrate Design-for-Trust (DfTr) techniques. These include security strategies such as circuit camouflaging and advanced logic locking. Polymorphic Logic Gates (PLGs) based on dual-doped RFET (DD-RFET) technology are designed and validated through mixed-mode simulations at both gate and circuit levels. To demonstrate practical applicability, camouflaging and an URSAT logic-locking scheme are implemented on a small benchmark circuit, and security is evaluated using custom brute-force and SAT-like attacks. While the limited circuit size allows efficient key recovery, results show non-trivial attack effort and significant output corruption for incorrect keys. In addition, DD-RFETs provide enhanced reconfigurability and potentially reduced transistor count compared to conventional CMOS implementations, making them suitable as complementary building blocks for Design-for-Trust applications and as a platform to explore security-oriented circuit design.},
organization = {MICIU / AEI (10.13039/501100011033) – (PID2020-119668GB-I00)(Grant PID2023-152467OA-I00)(PID2021-128547OB-I00)},
organization = {MICIU / AEI (10.13039/501100011033) + European Union – NextGenerationEU / PRTR – (PDC2023-145915-I00)},
organization = {Horizon Europe – MSCA (CONCEPT-2D) – (Grant +QCHIP TSI-069100-2023-0003)(Grant 101062995)},
publisher = {IEEE},
keywords = {DD-RFET},
keywords = {Dual doping},
keywords = {Design for trust},
title = {Dual-Doped Reconfigurable FETs for Hardware Security: A TCAD Approach},
doi = {10.1109/access.2026.3653483},
author = {Ortega, Ruben and Hervas, Antonio and Donetti, Luca and Martínez, Alberto and Márquez González, Carlos and Caño-García, Manuel and Gámiz Pérez, Francisco Jesús and Navarro Moral, Carlos},
}