Dual-Doped Reconfigurable FETs for Hardware Security: A TCAD Approach Ortega, Ruben Hervas, Antonio Donetti, Luca Martínez, Alberto Márquez González, Carlos Caño-García, Manuel Gámiz Pérez, Francisco Jesús Navarro Moral, Carlos DD-RFET Dual doping Design for trust A novel variant of reconfigurable FETs (RFETs), employing source and drain doped terminals instead of Schottky contacts, is explored through TCAD simulations for implementing logic circuits that integrate Design-for-Trust (DfTr) techniques. These include security strategies such as circuit camouflaging and advanced logic locking. Polymorphic Logic Gates (PLGs) based on dual-doped RFET (DD-RFET) technology are designed and validated through mixed-mode simulations at both gate and circuit levels. To demonstrate practical applicability, camouflaging and an URSAT logic-locking scheme are implemented on a small benchmark circuit, and security is evaluated using custom brute-force and SAT-like attacks. While the limited circuit size allows efficient key recovery, results show non-trivial attack effort and significant output corruption for incorrect keys. In addition, DD-RFETs provide enhanced reconfigurability and potentially reduced transistor count compared to conventional CMOS implementations, making them suitable as complementary building blocks for Design-for-Trust applications and as a platform to explore security-oriented circuit design. 2026-02-03T09:52:07Z 2026-02-03T09:52:07Z 2026-01-16 journal article Ortega, R., Hervás, A., Donetti, L., Martínez, A., Márquez, C., Caño-García, M., Gámiz, F., & Navarro, C. (2026). Dual-doped reconfigurable FETs for hardware security: A TCAD approach. IEEE Access: Practical Innovations, Open Solutions, 14, 8366–8374. https://doi.org/10.1109/access.2026.3653483 https://hdl.handle.net/10481/110610 10.1109/access.2026.3653483 eng info:eu-repo/grantAgreement/EU/PRTR/PDC2023-145915-I00 http://creativecommons.org/licenses/by/4.0/ open access Atribución 4.0 Internacional IEEE