A 2-D-Material FET Verilog-A Model for Analog Neuromorphic Circuit Design

Dubey, Prabhat Kumar; Strangio, Sebastiano; González Marín, Enrique; Iannaccone, Giuseppe; Fiori, Gianluca

doi:10.1109/TED.2023.3298876

A_2-D-Material_FET_Verilog.pdf (4.692Mo)

Identificadores

URI: https://hdl.handle.net/10481/84513

DOI: 10.1109/TED.2023.3298876

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Editorial

IEEE

Materia

2-D materials (2DMs)

Current mirror (CM)

Explicit compact model

Neural network

Vector-matrix multiplier (VMM)

Verilog-A model

Date

2023-08-07

Referencia bibliográfica

P. K. Dubey, S. Strangio, E. G. Marin, G. Iannaccone and G. Fiori, "A 2-D-Material FET Verilog-A Model for Analog Neuromorphic Circuit Design," in IEEE Transactions on Electron Devices, vol. 70, no. 9, pp. 4945-4952, Sept. 2023. [doi: 10.1109/TED.2023.3298876]

Patrocinador

European Project through European Research Council (ERC) Printable Electronic on Paper Through 2D Material based Inks (PEP2D) 770047; Origami Electronics for three-dimensional integration of computational devices (ORIGENAL) 828901; Quantum Engineering for Machine Learning (QUEFORMAL) 829035; MCIN/AEI PID2020-116518GB-I00; FEDER/Junta de Andalucia A-TIC-646-UGR20

Résumé

We present a charge-based Verilog-A model for 2-D-material (2DM)-based field-effect transistors (FETs) with application in neuromorphic circuit design. The model combines the explicit solution of the drift-diffusion transport and electrostatics, including Fermi-Dirac statistics. The Ward-Dutton linear charge partitioning scheme is then employed for terminal charges and capacitance calculations. The model accurately predicts the electrical behavior of experimental MoS2 FETs, and it is applied to simulate neuromorphic-circuit building blocks, including a floating-gate (FG) current-mirror (CM) vector-matrix multi-plier (VMM), extracting the effective number of bits under different operation conditions.

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