dc.contributor.author | Pérez-Bosch Quesada, Emilio | |
dc.contributor.author | Romero Zaliz, Rocio Celeste | |
dc.contributor.author | Jiménez Molinos, Francisco | |
dc.contributor.author | Roldán Aranda, Juan Bautista | |
dc.date.accessioned | 2021-04-27T09:56:30Z | |
dc.date.available | 2021-04-27T09:56:30Z | |
dc.date.issued | 2021-03-11 | |
dc.identifier.citation | Pérez-Bosch Quesada, E.; Romero-Zaliz, R.; Perez, E.; Kalishettyhalli Mahadevaiah, M.; Reuben, J.; Schubert, M.A., Jimenez-Molinos, F., Roldan, J.B.; Wenger, C. Toward Reliable Compact Modeling of Multilevel 1T-1R RRAM Devices for Neuromorphic Systems. Electronics 2021, 10, 645. [https://doi.org/10.3390/electronics10060645] | es_ES |
dc.identifier.uri | http://hdl.handle.net/10481/68147 | |
dc.description | The authors would like to thank the financial support by Deutsche Forschungsgemeinschaft
(German Research Foundation) with Project-ID SFB1461 and by the Federal Ministry of Education
and Research of Germany under grant numbers 16ES1002, 16FMD01K, 16FMD02 and 16FMD03.
The authors also gratefully acknowledge the support of the Spanish Ministry of Science, Innovation
and Universities and the FEDER program through project TEC2017-84321-C4-3-R and project
A.TIC.117.UGR18 funded by the government of Andalusia (Spain) and the FEDER program. The
publication of this article was funded by the Open Access Fund of the Leibniz Association. | es_ES |
dc.description | The datasets generated during and/or analysed during the current
study are available from the corresponding author on reasonable request. | es_ES |
dc.description.abstract | In this work, three different RRAM compact models implemented in Verilog-A are analyzed and evaluated in order to reproduce the multilevel approach based on the switching capability of experimental devices. These models are integrated in 1T-1R cells to control their analog behavior by means of the compliance current imposed by the NMOS select transistor. Four different resistance levels are simulated and assessed with experimental verification to account for their multilevel capability. Further, an Artificial Neural Network study is carried out to evaluate in a real scenario the viability of the multilevel approach under study. | es_ES |
dc.description.sponsorship | German Research Foundation (DFG)
SFB1461 | es_ES |
dc.description.sponsorship | Federal Ministry of Education & Research (BMBF)
16ES1002
16FMD01K
16FMD02
16FMD03 | es_ES |
dc.description.sponsorship | Spanish Ministry of Science, Innovation and Universities | es_ES |
dc.description.sponsorship | European Commission
TEC2017-84321-C4-3-R | es_ES |
dc.description.sponsorship | government of Andalusia (Spain)
A.TIC.117.UGR18 | es_ES |
dc.description.sponsorship | Leibniz Association | es_ES |
dc.language.iso | eng | es_ES |
dc.publisher | MDPI | es_ES |
dc.rights | Atribución 3.0 España | * |
dc.rights.uri | http://creativecommons.org/licenses/by/3.0/es/ | * |
dc.subject | RRAM | es_ES |
dc.subject | 1T-1R | es_ES |
dc.subject | Multilevel | es_ES |
dc.subject | Compact modeling | es_ES |
dc.subject | Verilog-A | es_ES |
dc.subject | Artificial neural network | es_ES |
dc.title | Toward Reliable Compact Modeling of Multilevel 1T-1R RRAM Devices for Neuromorphic Systems | es_ES |
dc.type | journal article | es_ES |
dc.rights.accessRights | open access | es_ES |
dc.identifier.doi | 10.3390/electronics10060645 | |
dc.type.hasVersion | VoR | es_ES |