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Toward Reliable Compact Modeling of Multilevel 1T-1R RRAM Devices for Neuromorphic Systems

dc.contributor.authorPérez-Bosch Quesada, Emilio
dc.contributor.authorRomero Zaliz, Rocio Celeste 
dc.contributor.authorJiménez Molinos, Francisco 
dc.contributor.authorRoldán Aranda, Juan Bautista 
dc.date.accessioned2021-04-27T09:56:30Z
dc.date.available2021-04-27T09:56:30Z
dc.date.issued2021-03-11
dc.identifier.citationPérez-Bosch Quesada, E.; Romero-Zaliz, R.; Perez, E.; Kalishettyhalli Mahadevaiah, M.; Reuben, J.; Schubert, M.A., Jimenez-Molinos, F., Roldan, J.B.; Wenger, C. Toward Reliable Compact Modeling of Multilevel 1T-1R RRAM Devices for Neuromorphic Systems. Electronics 2021, 10, 645. [https://doi.org/10.3390/electronics10060645]es_ES
dc.identifier.urihttp://hdl.handle.net/10481/68147
dc.descriptionThe authors would like to thank the financial support by Deutsche Forschungsgemeinschaft (German Research Foundation) with Project-ID SFB1461 and by the Federal Ministry of Education and Research of Germany under grant numbers 16ES1002, 16FMD01K, 16FMD02 and 16FMD03. The authors also gratefully acknowledge the support of the Spanish Ministry of Science, Innovation and Universities and the FEDER program through project TEC2017-84321-C4-3-R and project A.TIC.117.UGR18 funded by the government of Andalusia (Spain) and the FEDER program. The publication of this article was funded by the Open Access Fund of the Leibniz Association.es_ES
dc.descriptionThe datasets generated during and/or analysed during the current study are available from the corresponding author on reasonable request.es_ES
dc.description.abstractIn this work, three different RRAM compact models implemented in Verilog-A are analyzed and evaluated in order to reproduce the multilevel approach based on the switching capability of experimental devices. These models are integrated in 1T-1R cells to control their analog behavior by means of the compliance current imposed by the NMOS select transistor. Four different resistance levels are simulated and assessed with experimental verification to account for their multilevel capability. Further, an Artificial Neural Network study is carried out to evaluate in a real scenario the viability of the multilevel approach under study.es_ES
dc.description.sponsorshipGerman Research Foundation (DFG) SFB1461es_ES
dc.description.sponsorshipFederal Ministry of Education & Research (BMBF) 16ES1002 16FMD01K 16FMD02 16FMD03es_ES
dc.description.sponsorshipSpanish Ministry of Science, Innovation and Universitieses_ES
dc.description.sponsorshipEuropean Commission TEC2017-84321-C4-3-Res_ES
dc.description.sponsorshipgovernment of Andalusia (Spain) A.TIC.117.UGR18es_ES
dc.description.sponsorshipLeibniz Associationes_ES
dc.language.isoenges_ES
dc.publisherMDPIes_ES
dc.rightsAtribución 3.0 España*
dc.rights.urihttp://creativecommons.org/licenses/by/3.0/es/*
dc.subjectRRAMes_ES
dc.subject1T-1Res_ES
dc.subjectMultileveles_ES
dc.subjectCompact modelinges_ES
dc.subjectVerilog-Aes_ES
dc.subjectArtificial neural networkes_ES
dc.titleToward Reliable Compact Modeling of Multilevel 1T-1R RRAM Devices for Neuromorphic Systemses_ES
dc.typejournal articlees_ES
dc.rights.accessRightsopen accesses_ES
dc.identifier.doi10.3390/electronics10060645
dc.type.hasVersionVoRes_ES


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