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dc.contributor.authorDonetti, Luca 
dc.contributor.authorMedina Bailón, Cristina 
dc.contributor.authorPadilla De la Torre, José Luis 
dc.contributor.authorSampedro Matarín, Carlos 
dc.contributor.authorGámiz Pérez, Francisco Jesús 
dc.date.accessioned2026-01-26T09:23:56Z
dc.date.available2026-01-26T09:23:56Z
dc.date.issued2025
dc.identifier.citationIEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 72, NO. 6, P. 2727es_ES
dc.identifier.urihttps://hdl.handle.net/10481/110243
dc.description.abstractThe capacitance of the gate oxide is a crucial parameter to model the performance of MOSFETs. The traditional expression used to compute it stems from the parallel-plate capacitor formula. While its use is appropriate for planar devices, it has been naturally extended to 3-D devices such as those based on nanosheets even if the geometry is quite different. In this work, we compute numerically the gate oxide capacitance of nanosheet transistors and, observing a nonnegligible discrepancy with the planar model, we propose a simple model that better reproduces the computed capacitance. Then, we investigate the definition of equivalent oxide thickness (EOT), showing that it cannot be strictly used for nonplanar devices: however, our improved model allows us to obtain a useful expression valid for the most common cases. Finally, we generalize the capacitance model to nanosheets with rounded corners.es_ES
dc.language.isospaes_ES
dc.rightsAtribución 4.0 Internacional*
dc.rights.urihttp://creativecommons.org/licenses/by/4.0/*
dc.subjectEquivalent oxide thickness (EOT)es_ES
dc.subjectgate insulator capacitancees_ES
dc.subjectgate-all-around (GAA)es_ES
dc.subjectMOSFETes_ES
dc.subjectnanosheet MOSFETes_ES
dc.titleOn the Capacitance of Nanosheet Transistorses_ES
dc.typejournal articlees_ES
dc.rights.accessRightsopen accesses_ES
dc.identifier.doi10.1109/TED.2025.3559482


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Atribución 4.0 Internacional
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