A Compact Charge and Surface Potential Model for III–V Cylindrical Nanowire Transistors
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III–V circuit simulation compactmodeling MOS transistor nanowire (NW) quantum capacitance
Fecha
2019-01-01Resumen
Considering the demand of III–V multigate (MUG) transistors for next-generation CMOS technologies, a compactmodel is required to test their performance in different circuits. The low effective mass and highly confined geometry of these MUG devices demand the use of computationally expensive coupled Poisson–Schrödinger (PS) solver for terminal charges and surface potential. In this paper, we propose an approximation, which decouples the PS equations and enables the development of a computationally efficient analytical model. The surface potential and semiconductor charge equations for III–V low effective mass channel cylindrical nanowire (NW) transistors are derived using the proposed approximation. The proposed model is physics based and does not include any empirical parameters. The accuracy of the model is verified across NWs of different sizes andmaterials using the data fromthe 2-D PS solver and found to be accurate.





