On the Low-Frequency Noise Characterization of Z2-FET Devices
Metadatos
Afficher la notice complèteAuteur
Marquez, Carlos; Navarro, Carlos; Navarro, Santiago; Padilla De la Torre, José Luis; Donetti, Luca; Sampedro Matarín, Carlos; Galy, Philippe; Kim, Yong Tae; Gámiz Pérez, Francisco JesúsEditorial
IEEE
Materia
Noise measurement Semiconductor device reliability Silicon on insulator technology
Date
2019-03-22Referencia bibliográfica
Marquez, C., Navarro, C., Navarro, S., Padilla, J. L., Donetti, L., Sampedro, C., ... & Gamiz, F. (2019). On the Low-Frequency Noise Characterization of Z 2-FET Devices. IEEE Access, 7, 42551-42556.
Patrocinador
This work was supported in part by the European REMINDER 687931 Grant, in part by the Consejeria de Economia, Conocimiento, Empresas y Universidad de la Junta de Andalucia and European Regional Development Fund (ERDF), under Grant SOMM17/6109/ UGR, and in part by the TEC2017-89800-R ProjectsRésumé
This paper addresses the low-frequency noise characterization of Z2-FET structures. These
double-gated p-i-n diode devices have been fabricated at STMicroelectronics in an ultrathin body and
box (UTBB) 28-nm FDSOI technology and designed to operate as 1T-DRAM memory cells, although
other applications, as for example electro static discharge (ESD) protection, have been reported. The
experimentally extracted power spectral density of current reveals that the high-diode series resistance,
carrier number fluctuations due to oxide traps, and gate leakage current are the main noise contributors
at high-current regimes. These mechanisms are expected to contribute to the degradation of cell variability
and retention time. Higher flicker noise levels have been reported when increasing the vertical electric field.
A simple model considering the contribution of the main noise sources is proposed.