Wafer-Scale Demonstration of BEOL-Compatible Ambipolar MoS2 Devices Enabled by Plasma-Enhanced Atomic Layer Deposition
Metadata
Show full item recordAuthor
Martínez, Alberto; Márquez González, Carlos; Lorenzo Lazaro, Francisco; Gutierrez Parejo, Francisco; Caño-García, Manuel; Ávila Gómez, Jorge Pablo; Galdón Gil, José Carlos; Ortega López, Rubén; Navarro Moral, Carlos; Donetti, Luca; Gámiz Pérez, Francisco JesúsEditorial
American Chemical Society
Date
2025-09Referencia bibliográfica
Alberto Martínez, Carlos Márquez, Francisco Lorenzo, Francisco Gutiérrez, Manuel Caño-García, Jorge Ávila, José Carlos Galdón Gil, Ruben Ortega Lopez, Carlos Navarro, Luca Donetti, and Francisco Gámiz ACS Applied Materials & Interfaces 2025 17 (37), 52902-52912 DOI: 10.1021/acsami.5c12014
Sponsorship
This research was partially funded by The C-ING-357-UGR23 project, supported by the Andalusian University, Investigation and Innovation Council, and the EU FEDER Andalucia 2021-2027, and the Spanish projects MICIU/AEI PID2023-152467OA-I00, MCIN/AEI PID2021-128547OB-I00, and MICIU/AEI PLEC2022-009381, with backing from the European Union NextGeneration EU/PRTR. M.C. acknowledges the financial support from the CONCEPT-2D MSCA project (Grant Agreement No. 101062995). The +QCHIP TSI-069100-2023-0003, HORIZON-JU-GH-EDCTP3-2023-01 (EPOCA Grant 101145795) and HORIZON-JU-Chips-2023-RIA-CPL-2 (FAMES ID 101182279) projects are also acknowledged for their financial support. Funding for open access charge: Universidad de Granada / CBUA.Abstract
The relentless scaling of semiconductor technology demands materials beyond silicon to sustain performance improvements. Transition metal dichalcogenides (TMDs), particularly MoS2, offer excellent electronic properties; however, achieving scalable and CMOS-compatible fabrication remains a critical challenge. Here, we demonstrate a scalable and BEOL-compatible approach for the direct wafer-scale growth of MoS2 devices using plasma-enhanced atomic layer deposition (PE-ALD) at temperatures below 450 °C, fully compliant with CMOS thermal budgets. This method enables the fabrication of MoS2-based devices directly on target substrates, eliminating material transfer while ensuring robust adhesion and integration with semiconductor processing. The resulting field-effect transistors (FETs) exhibit stable ambipolar behavior, consistent across semiconductor thickness variations and environmental conditions. Electrical characterization reveals minimal Fermi-level pinning, with Schottky barrier heights below 120 meV for both carriers, supporting a well-defined thermionic transport regime. Low-frequency noise measurements confirm flicker noise characteristics, typical of planar field-effect devices. Material conductivity is significantly enhanced through in situ, BEOL-compatible dielectric passivation or sulfur-atmosphere annealing. This work highlights the potential to directly fabricate, lithographically pattern, and encapsulate MoS2 devices for three-dimensional (3D) integration, fully compliant with silicon CMOS thermal constraints.





