TY  - GEN 
AU  - Hatefinasab, Seyedehsomayeh
AU  - Salinas Castillo, Alfonso
AU  - Castillo Morales, María Encarnación
AU  - Rodríguez Santiago, Noel
PY  - 2022
UR  - http://hdl.handle.net/10481/74320
AB  - As CMOS technology scaling pushes towards the reduction of the length of transistors,
electronic circuits face numerous reliability issues, and in particular nodes of D-latches at nano-scale confront
multiple-node upset errors due to their operation...
LA  - eng
PB  - IEEE
KW  - Power-delay product (PDP)
KW  - Soft errors (SE)
KW  - Single event upset (SEU)
KW  - High impedance state (HIS)
KW  - Single event transient (SET)
KW  - Dual interlocked storage cell (DICE)
KW  - Triple path DICE (TPDICE)
KW  - Quadruple-node upsets (QNUs)
TI  - Highly Reliable Quadruple-Node Upset-Tolerant D-Latch
DO  - 10.1109/ACCESS.2022.3160448
ER  -