TY  - JOUR 
AU  - Hatefinasab, Seyedehsomayeh
AU  - Rodríguez Santiago, Noel
AU  - García Ríos, Antonio
AU  - Castillo Morales, María Encarnación
PY  - 2021
UR  - http://hdl.handle.net/10481/68712
AB  - In this paper, a Soft Error Hardened D-latch with improved performance is proposed, also
featuring Single Event Upset (SEU) and Single Event Transient (SET) immunity. This novel D-latch
can tolerate particles as charge injection in different...
LA  - eng
PB  - MDPI
KW  - Hardened D-latch
KW  - Complementary Metal Oxide Semiconductor (CMOS) technology
KW  - Power-Delay Product (PDP)
KW  - Soft Error (SE)
KW  - SEU (Single Event Upset)
KW  - High Impedance State (HIS)
KW  - Single event transient (SET)
TI  - Low-Cost Soft Error Robust Hardened D-Latch for CMOS Technology Circuit
DO  - 10.3390/electronics10111256
ER  -