Memory Operation of Z2-FET Without Selector at High Temperature Kwon, S. Navarro Moral, Carlos Gámiz Pérez, Francisco Jesús Matrix memory operation High temperature Z2-FET 1T-DRAM This work was supported in part by the REMINDER European Project under Grant 687931; in part by the Ministry of Trade, Industry, & Energy (MOTIE)under Grant 10080526; and in part by the Korea Semiconductor Research Consortium (KSRC) Support Program for the development of future semiconductor devices. The electrical performance of Z2-FET and memory operations of matrix are demonstrated at high temperatures up to 125 ◦C. The sharp subthreshold slope is maintained and the reliable operation is ensured within the memory window of 229 mV even though the turn on voltage of ‘0’- and ‘1’-states are shifted to lower voltage. The ‘0’-state current remains low while the ‘1’-state current gradually increases as the temperature increases leading to higher current margin. At the elevated temperature, the potential barriers are slightly reduced but does not collapse, which leads to the successful memory operation. However, increasing the temperature over 125 ◦C, the potential barrier at the ‘0’-state is significantly reduced and causes the failure of memory operation with high ‘0’-state current. The matrix demonstrates reliable memory operations without using selector circuits even at 125 ◦C. 2021-09-14T11:15:30Z 2021-09-14T11:15:30Z 2021-07-02 info:eu-repo/semantics/article S. Kwon... [et al.]. "Memory Operation of Z²-FET Without Selector at High Temperature," in IEEE Journal of the Electron Devices Society, vol. 9, pp. 658-662, 2021, doi: [10.1109/JEDS.2021.3094104] http://hdl.handle.net/10481/70206 10.1109/JEDS.2021.3094104 eng info:eu-repo/grantAgreement/EC/H2020/687931 http://creativecommons.org/licenses/by/3.0/es/ info:eu-repo/semantics/openAccess Atribución 3.0 España IEEE