On the Low-Frequency Noise Characterization of Z2-FET Devices Marquez, Carlos Navarro, Carlos Navarro, Santiago Padilla De la Torre, José Luis Donetti, Luca Sampedro Matarín, Carlos Galy, Philippe Kim, Yong Tae Gámiz Pérez, Francisco Jesús Noise measurement Semiconductor device reliability Silicon on insulator technology This paper addresses the low-frequency noise characterization of Z2-FET structures. These double-gated p-i-n diode devices have been fabricated at STMicroelectronics in an ultrathin body and box (UTBB) 28-nm FDSOI technology and designed to operate as 1T-DRAM memory cells, although other applications, as for example electro static discharge (ESD) protection, have been reported. The experimentally extracted power spectral density of current reveals that the high-diode series resistance, carrier number fluctuations due to oxide traps, and gate leakage current are the main noise contributors at high-current regimes. These mechanisms are expected to contribute to the degradation of cell variability and retention time. Higher flicker noise levels have been reported when increasing the vertical electric field. A simple model considering the contribution of the main noise sources is proposed. 2020-02-10T08:34:16Z 2020-02-10T08:34:16Z 2019-03-22 journal article Marquez, C., Navarro, C., Navarro, S., Padilla, J. L., Donetti, L., Sampedro, C., ... & Gamiz, F. (2019). On the Low-Frequency Noise Characterization of Z 2-FET Devices. IEEE Access, 7, 42551-42556. http://hdl.handle.net/10481/59522 10.1109/ACCESS.2019.2907062 eng http://creativecommons.org/licenses/by-nc-nd/3.0/es/ open access Atribución-NoComercial-SinDerivadas 3.0 España IEEE