Real-Time System for High-Image Resolution Disparity Estimation Díaz Alonso, Antonio Javier Ros Vidal, Eduardo Carrillo Sánchez, Richard Rafael Prieto Espinosa, Alberto pipeline processing scale space stereo image processing embedded and real-time systems We present the hardware implementation of a simple, fast technique for depth estimation based on phase measurement. This technique avoids the problem of phase warping and is much less susceptible to camera noise and distortion than standard block-matching stereo systems. The architecture exploits the parallel computing resources of FPGA devices to achieve a computation speed of 65 megapixels per second. For this purpose, we have designed a fine-grain pipeline structure that can be arranged with a customized frame-grabber module to process 52 frames per second at a resolution of 1280 x 960 pixels. We have measured the system's degradation due to bit quantization errors and compared its performance with other previous approaches. We have also used different Gabor-scale circuits, which can be selected by the user according to the application addressed and typical image structure in the target scenario. 2025-02-01T12:53:03Z 2025-02-01T12:53:03Z 2006-12-19 journal article Published version: Diaz, J., Ros, E., Carrillo, R., & Prieto, A. (2006). Real-time system for high-image resolution disparity estimation. IEEE Transactions on Image Processing, 16(1), 280-285. doi: 10.1109/TIP.2006.884931 https://hdl.handle.net/10481/101734 10.1109/TIP.2006.884931 eng http://creativecommons.org/licenses/by-nc-nd/4.0/ open access Attribution-NonCommercial-NoDerivatives 4.0 Internacional IEEE