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Hardware Implementations of a Deep Learning Approach to Optimal Configuration of Reconfigurable Intelligence Surfaces
dc.contributor.author | Martín Martín, Alberto | |
dc.contributor.author | Padial-Allué, Rubén | |
dc.contributor.author | Castillo Morales, María Encarnación | |
dc.contributor.author | Parrilla Roure, Luis | |
dc.contributor.author | Parellada Serrano, Ignacio | |
dc.contributor.author | Morán, Alejandro | |
dc.contributor.author | García Ríos, Antonio | |
dc.date.accessioned | 2024-02-09T11:37:11Z | |
dc.date.available | 2024-02-09T11:37:11Z | |
dc.date.issued | 2024-01-30 | |
dc.identifier.uri | https://hdl.handle.net/10481/88857 | |
dc.description.abstract | Reconfigurable intelligent surfaces (RIS) offer the potential to customize the radio propagation environment for wireless networks, and will be a key element for 6G communications. However, due to the unique constraints in these systems, the optimization problems associated to RIS configuration are challenging to solve. This paper illustrates a new approach to the RIS configuration problem, based on the use of artificial intelligence (AI) and deep learning (DL) algorithms. Concretely, a custom convolutional neural network (CNN) intended for edge computing is presented, and implementations on different representative edge devices are compared, including the use of commercial AI-oriented devices and a field-programmable gate array (FPGA) platform. This FPGA option provides the best performance, with x20 performance increase over the closest FP32, GPU-accelerated option, and almost x3 performance advantage when compared with the INT8-quantized, TPU-accelerated implementation. More noticeably, this is achieved even when high-level synthesis (HLS) tools are used and no custom accelerators are developed. At the same time, the inherent reconfigurability of FPGAs opens a new field for their use as enabler hardware in RIS applications. | es_ES |
dc.description.sponsorship | This work is part of the project TED2021-129938B-I00, funded by MCIN/AEI/10.13039/501100011033 and by the European Union NextGenerationEU/PRTR. | es_ES |
dc.language.iso | eng | es_ES |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | 6G | es_ES |
dc.subject | Reconfigurable Intelligent Surfaces | es_ES |
dc.subject | Artificial Intelligence | es_ES |
dc.subject | Neural Networks | es_ES |
dc.subject | FPGA | es_ES |
dc.title | Hardware Implementations of a Deep Learning Approach to Optimal Configuration of Reconfigurable Intelligence Surfaces | es_ES |
dc.type | journal article | es_ES |
dc.rights.accessRights | open access | es_ES |
dc.identifier.doi | 10.3390/s24030899 | |
dc.type.hasVersion | VoR | es_ES |