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Highly Reliable Quadruple-Node Upset-Tolerant D-Latch
dc.contributor.author | Hatefinasab, Seyedehsomayeh | |
dc.contributor.author | Salinas Castillo, Alfonso | |
dc.contributor.author | Castillo Morales, María Encarnación | |
dc.contributor.author | Rodríguez Santiago, Noel | |
dc.date.accessioned | 2022-04-18T10:06:10Z | |
dc.date.available | 2022-04-18T10:06:10Z | |
dc.date.issued | 2022-03-17 | |
dc.identifier.citation | S. Hatefinasab... [et al.]. "Highly Reliable Quadruple-Node Upset-Tolerant D-Latch," in IEEE Access, vol. 10, pp. 31836-31850, 2022, doi: [10.1109/ACCESS.2022.3160448] | es_ES |
dc.identifier.uri | http://hdl.handle.net/10481/74320 | |
dc.description | This work was supported in part by the Spanish MCIN/AEI /10.13039/501100011033/ FEDER under Grant PID2020-117344RB-I00, and in part by the Regional Government under Grant P20_00265 and Grant P20_00633. | es_ES |
dc.description.abstract | As CMOS technology scaling pushes towards the reduction of the length of transistors, electronic circuits face numerous reliability issues, and in particular nodes of D-latches at nano-scale confront multiple-node upset errors due to their operation in harsh radiative environments. In this manuscript, a new high reliable D-latch which can tolerate quadruple-node upsets is presented. The design is based on a low-cost single event double-upset tolerant (LSEDUT) cell and a clock-gating triple-level soft-error interceptive module (CG-SIM). Due to its LSEDUT base, it can tolerate two upsets, but the combination of two LSEDUTs and the triple-level CG-SIM provides the proposed D-latch with remarkable quadruple-node upsets (QNU) tolerance. Applying LSEDUTs for designing a QNU-tolerant D-latch improves considerably its features; in particular, this approach enhances its reliability against process variations, such as threshold voltage and (W/L) transistor variability, compared to previous QNU-tolerant D-latches and double-node-upset tolerant latches. Furthermore, the proposed D-latch not only tolerates QNUs, but it also features a clear advantage in comparison with the previous clock gating-based quadruple-node-upset-tolerant (QNUTL-CG) D-latch: it can mask single event transients. Speci c gures of merit endorse the gains introduced by the new design: compared with the QNUTL-CG D-latch, the improvements of the maximum standard deviations of the gate delay, induced by threshold voltage and (W/L) transistors variability of the proposed D-latch, are 13.8% and 5.7%, respectively. Also, the proposed D-latch has 23% lesser maximum standard deviation in power consumption, resulting from threshold voltage variability, when compared to the QNUTL-CG D-latch. | es_ES |
dc.description.sponsorship | Spanish MCIN/AEI /10.13039/501100011033/ FEDER under Grant PID2020-117344RB-I00 | es_ES |
dc.description.sponsorship | Regional Government under Grant P20_00265 and Grant P20_00633 | es_ES |
dc.language.iso | eng | es_ES |
dc.publisher | IEEE | es_ES |
dc.rights | Atribución 3.0 España | * |
dc.rights.uri | http://creativecommons.org/licenses/by/3.0/es/ | * |
dc.subject | Power-delay product (PDP) | es_ES |
dc.subject | Soft errors (SE) | es_ES |
dc.subject | Single event upset (SEU) | es_ES |
dc.subject | High impedance state (HIS) | es_ES |
dc.subject | Single event transient (SET) | es_ES |
dc.subject | Dual interlocked storage cell (DICE) | es_ES |
dc.subject | Triple path DICE (TPDICE) | es_ES |
dc.subject | Quadruple-node upsets (QNUs) | es_ES |
dc.title | Highly Reliable Quadruple-Node Upset-Tolerant D-Latch | es_ES |
dc.type | journal article | es_ES |
dc.rights.accessRights | open access | es_ES |
dc.identifier.doi | 10.1109/ACCESS.2022.3160448 | |
dc.type.hasVersion | VoR | es_ES |