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dc.contributor.authorPérez Ávila, Antonio Javier
dc.contributor.authorRomero Zaliz, Rocio Celeste 
dc.contributor.authorRoldán Aranda, Juan Bautista 
dc.contributor.authorJiménez Molinos, Francisco 
dc.date.accessioned2021-05-06T08:31:09Z
dc.date.available2021-05-06T08:31:09Z
dc.date.issued2021
dc.identifier.citationPérez, E.; Pérez-Ávila, A.J.; Romero-Zaliz, R.; Mahadevaiah, M.K.; Pérez-Bosch Quesada, E.; Roldán, J.B.; Jiménez-Molinos, F.; Wenger, C. Optimization of Multi-Level Operation in RRAM Arrays for In-Memory Computing. Electronics 2021, 10, 1084. https:// doi.org/10.3390/electronics10091084es_ES
dc.identifier.urihttp://hdl.handle.net/10481/68355
dc.description.abstractAccomplishing multi-level programming in resistive random access memory (RRAM) arrays with truly discrete and linearly spaced conductive levels is crucial in order to implement synaptic weights in hardware-based neuromorphic systems. In this paper, we implemented this feature on 4-kbit 1T1R RRAM arrays by tuning the programming parameters of the multi-level incremental step pulse with verify algorithm (M-ISPVA). The optimized set of parameters was assessed by comparing its results with a non-optimized one. The optimized set of parameters proved to be an effective way to define non-overlapped conductive levels due to the strong reduction of the device-to-device variability as well as of the cycle-to-cycle variability, assessed by inter-levels switching tests and during 1k reset-set cycles. In order to evaluate this improvement in real scenarios, the experimental characteristics of the RRAM devices were captured by means of a behavioral model, which was used to simulate two different neuromorphic systems: an 8×8 vector-matrixmultiplication (VMM) accelerator and a 4-layer feedforward neural network for MNIST database recognition. The results clearly showed that the optimization of the programming parameters improved both the precision of VMM results as well as the recognition accuracy of the neural network in about 6% compared with the use of non-optimized parameters.es_ES
dc.description.sponsorshipGerman Research Foundation (DFG) - FOR2093es_ES
dc.description.sponsorshipGovernment of Andalusia (Spain) and the FEDER program in the frame of the project A.TIC.117.UGR18es_ES
dc.description.sponsorshipOpen Access Fund of the Leibniz Associationes_ES
dc.language.isoenges_ES
dc.publisherMDPIes_ES
dc.rightsAtribución 3.0 España*
dc.rights.urihttp://creativecommons.org/licenses/by/3.0/es/*
dc.subjectRRAM arrayses_ES
dc.subjectProgramming algorithmes_ES
dc.subjectMulti-leveles_ES
dc.subjectInter-levels switchinges_ES
dc.subjectIn-memory computinges_ES
dc.subjectVector-matrix-multiplicationes_ES
dc.titleOptimization of Multi-Level Operation in RRAM Arrays for In-Memory Computinges_ES
dc.typeinfo:eu-repo/semantics/articlees_ES
dc.rights.accessRightsinfo:eu-repo/semantics/openAccesses_ES
dc.identifier.doi10.3390/electronics10091084


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Atribución 3.0 España
Except where otherwise noted, this item's license is described as Atribución 3.0 España