A Scalable Physics-Based Compact Model for Terminal Charge, Intrinsic Capacitance and Drain Current in Nanosheet Field Effect Transistors

Abstract

This study introduces a physics-based, SPICE-compatible model for Nanosheet Field-Effect Transistors (NsFETs) that offers explicit expressions for the drain current, terminal charges, and intrinsic capacitances applicable to both p-type and n-type devices. The carrier transport is modeled using the drift-diffusion formalism, while the terminal charges are calculated using the Ward-Dutton linear charge partition scheme, ensuring charge conservation. Employing a bottom-up approach, the model effectively captures quantum mechanical confinement-induced effects with minimal reliance on empirical parameters, thus preserving the simplicity characteristic of traditional bulk MOSFET models. Short channel effects are modeled in a self-consistent way. This model has been extensively validated against both experimental data and simulations across varying device dimensions and bias conditions, demonstrating exceptional scalability across all device dimensions. The proposed model has also been implemented in Verilog-A and integrated in a commercial SPICE simulator to simulate NsFETs based circuits, underscoring the model’s practical applicability in contemporary semiconductor design.