@misc{10481/74320,
year = {2022},
month = {3},
url = {http://hdl.handle.net/10481/74320},
abstract = {As CMOS technology scaling pushes towards the reduction of the length of transistors,
electronic circuits face numerous reliability issues, and in particular nodes of D-latches at nano-scale confront
multiple-node upset errors due to their operation in harsh radiative environments. In this manuscript, a new
high reliable D-latch which can tolerate quadruple-node upsets is presented. The design is based on a low-cost
single event double-upset tolerant (LSEDUT) cell and a clock-gating triple-level soft-error interceptive
module (CG-SIM). Due to its LSEDUT base, it can tolerate two upsets, but the combination of two LSEDUTs
and the triple-level CG-SIM provides the proposed D-latch with remarkable quadruple-node upsets (QNU)
tolerance. Applying LSEDUTs for designing a QNU-tolerant D-latch improves considerably its features;
in particular, this approach enhances its reliability against process variations, such as threshold voltage and
(W/L) transistor variability, compared to previous QNU-tolerant D-latches and double-node-upset tolerant
latches. Furthermore, the proposed D-latch not only tolerates QNUs, but it also features a clear advantage
in comparison with the previous clock gating-based quadruple-node-upset-tolerant (QNUTL-CG) D-latch:
it can mask single event transients. Speci c  gures of merit endorse the gains introduced by the new design:
compared with the QNUTL-CG D-latch, the improvements of the maximum standard deviations of the gate
delay, induced by threshold voltage and (W/L) transistors variability of the proposed D-latch, are 13.8%
and 5.7%, respectively. Also, the proposed D-latch has 23% lesser maximum standard deviation in power
consumption, resulting from threshold voltage variability, when compared to the QNUTL-CG D-latch.},
organization = {Spanish MCIN/AEI /10.13039/501100011033/ FEDER under Grant PID2020-117344RB-I00},
organization = {Regional Government under Grant P20_00265 and Grant P20_00633},
publisher = {IEEE},
keywords = {Power-delay product (PDP)},
keywords = {Soft errors (SE)},
keywords = {Single event upset (SEU)},
keywords = {High impedance state (HIS)},
keywords = {Single event transient (SET)},
keywords = {Dual interlocked storage cell (DICE)},
keywords = {Triple path DICE (TPDICE)},
keywords = {Quadruple-node upsets (QNUs)},
title = {Highly Reliable Quadruple-Node Upset-Tolerant D-Latch},
doi = {10.1109/ACCESS.2022.3160448},
author = {Hatefinasab, Seyedehsomayeh and Salinas Castillo, Alfonso and Castillo Morales, María Encarnación and Rodríguez Santiago, Noel},
}