@misc{10481/61980,
year = {2019},
url = {http://hdl.handle.net/10481/61980},
abstract = {From a modeling point of view, the inclusion of adequate
physical phenomena is mandatory when analyzing the behavior of new
transistor architectures. In particular, the high electric field across the
ultra-thin insulator in aggressively scaled transistors leads to the possibility
for the charge carriers in the channel to tunnel through the gate oxide
via various gate leakage mechanisms (GLMs). In this work, we study the
impact of trap number on gate leakage using the GLM model, which is included
in a Multi-Subband Ensemble Monte Carlo (MS-EMC) simulator
for Fully-Depleted Silicon-On-Insulator (FDSOI) field effect transistors
(FETs). The GLM code described herein considers both direct and trap-assisted
tunneling. This work shows that trap attributes and dynamics
can modify the device electrostatic characteristics and even play a significant role in determining the extent of GLMs.},
organization = {The research leading to these results has received funding from the European Union's
Horizon 2020 research and innovation programme under grant agreement No 688101
SUPERAID7.},
publisher = {Springer Nature},
keywords = {Gate leakage mechanism},
keywords = {Direct tunneling},
keywords = {Trap assisted tunneling},
title = {Impact of the Trap Attributes on the Gate Leakage Mechanisms in a 2D MS-EMC Nanodevice Simulator},
doi = {10.1007/978-3-030-10692-8_30},
author = {Medina Bailón, Cristina and Sadi, T. and Sampedro Matarín, Carlos and Padilla García, José Luis and Donetti, Luca and Georgiev, Vihar and Gámiz Pérez, Francisco Jesús and Asenov, Asen},
}