@misc{10481/47952,
year = {2017},
month = {11},
url = {http://hdl.handle.net/10481/47952},
abstract = {The Z2-FET operation as capacitorless DRAM is analyzed using advanced 2-D TCAD simulations for IoT applications. The simulated architecture is built based on actual 28-nm fully depleted silicon-on-insulator devices. It is found that the triggering mechanism is dominated by the front-gate bias and the carrier’s diffusion length. As in other FB-DRAMs, the memory window is defined by the ON voltage shift with the stored body charge. However, the Z2-FET’s memory state is not exclusively defined by the inner charge but also by the reading conditions.},
publisher = {Institute of Electrical and Electronics Engineers (IEEE)},
keywords = {Semiconductor memories},
keywords = {Low-power},
keywords = {T-Dram},
keywords = {Capacitorless},
keywords = {Feedback effect},
keywords = {Fully depleted (FD)},
keywords = {Ground plane},
keywords = {Lifetime},
keywords = {Sharp switch},
keywords = {Silicon-on-insulator},
keywords = {Z2-FET},
title = {Extended analysis of the Z2-FET: Operation as capacitor-less eDRAM},
doi = {10.1109/TED.2017.2751141},
author = {Navarro Moral, Carlos and Lacord, Joris and Parihar, Mukta Singh and Adamu-Lema, Fikru and Duan, Meng and Rodríguez Santiago, Noel and Cheng, Binjie and El Dirani, Hassam and Barbe, Jean-Charles and Fonteneau, Pascal and Bawedin, Maryline and Millar, Campbell and Galy, Philippe and Le Royer, Cyrille and Karg, Sigfried and Wells, Paul and Kim, Yong Tae and Asenov, Asen and Cristoloveanu, Sorin and Gámiz Pérez, Francisco Jesús},
}