@misc{10481/110975,
year = {2026},
month = {2},
url = {https://hdl.handle.net/10481/110975},
abstract = {This paper proposes a power-of-two-based quantization technique aimed at improving
the hardware efficiency of artificial neural networks (ANNs) implemented on field
programmablegatearrays(FPGAs). Theeffectivenessoftheproposedapproachisvalidated
using gated recurrent unit (GRU) models. The resulting architecture, referred to as 2QGRU,
exploits parallelism, optimized operation scheduling, and fine-grained data bit-width
management to achieve efficient hardware realization. Compared with state-of-the-art
FPGA implementations based on sparsity compression, 2QGRU demonstrates superior
performance in terms of resource utilization and power consumption, while eliminating
the need for dedicated DSP blocks. Furthermore, area and power efficiency can be further
improved by trading latency for reduced hardware cost through an integrated implemen
tation reduction strategy, enabling deployment on highly resource-constrained devices.
Finally, the 2QGRU model is integrated into an automated ANN framework, allowing the
proposed quantization and hardware optimization techniques to be readily extended to
other ANNmodels and FPGA-based deployments.},
organization = {Key Digital Technologies Joint Undertaking (JU) - (No. 101112268 NEUROKIT2E)},
organization = {German Federal Ministry of Education and Research (BMBF) - (16MEE0300)},
publisher = {MDPI},
keywords = {Field programmable gate arrays},
keywords = {Power- and resource-constrained devices},
keywords = {Quantization},
title = {2QGRU: Power-of-Two Quantization for Efficient FPGA-Based Gated Recurrent Unit Architectures},
doi = {10.3390/electronics15040722},
author = {Molina Fernández, Luis Miguel and Hu Chen, Shao Jie and Méndez Gómez, Javier and Morales Santos, Diego Pedro and Pegalajar Cuéllar, Manuel and López Vallejo, Marisa},
}