@misc{10481/107467,
year = {2025},
month = {4},
url = {https://hdl.handle.net/10481/107467},
abstract = {In this work, a scalable technique is presented for the direct growth of tungsten disulfide (WS2) utilized in back-gated field-effect transistors (FETs), demonstrating robust and persistent p-type behavior across diverse conditions. Notably, this p-type behavior is consistently observed regardless of the metal contacts, semiconductor thickness, or ambient conditions, and remains stable even after high-vacuum and high-temperature annealing. Electrical characterization reveals negligible Fermi-level pinning at the conduction band edge, with minimal Schottky barrier heights for hole carriers below 180 mV and a well-defined thermionic transport regime. The devices exhibit field-effect mobilities with a clear back-gate dependence, reaching values up to 0.1 cm2V−1s−1. Temperature-dependent transport analysis indicates that charge carrier mobility is predominantly limited by impurity scattering and Coulomb interactions. First-principles simulations corroborate that the persistent p-type behavior could be driven by the presence of tungsten vacancies or WO3 oxide species. This study highlights the potential of WS2 for scalable integration into advanced p-type electronic devices and provides critical insights into the intrinsic mechanisms governing its charge transport properties.},
organization = {This research was partially funded by: The C-ING-357-UGR23 project, supported by Consejería de Universidad, Investigación e Innovación and by ERDF Andalusia Program 2021-2027, and the Spanish MICIU/AEI/10.13039/501100011033 projects PID2023-152467OA-I00, PID2021-128547OB-I00, and PLEC2022-009381, with backing from the ERDF/EU and European Union NextGeneration EU/PRTR, respectively. Device fabrication was carried out as part of the European Union Horizon 2020 project ASCENT+, under Grant Agreement no. 871130. The authors also acknowledged the support of Science Foundation Ireland (SFI), through the AMBER Research Centre (SFI-12/RC/2278_P2), as well as the Irish Research Council (IRC) for the EPSPG/2023/1772 project. The SFI/HEA Irish Centre for High-End Computing (ICHEC) is thanked for the provision of computational facilities and support for the DFT simulations. M.C. acknowledged the financial support from the CONCEPT-2D MSCA project (Grant Agreement No. 101062995). The +QCHIP TSI-069100-2023-0003, HORIZON-JU-GH-EDCTP3-2023-01 (EPOCA Grant 101145795) and HORIZON-JU-Chips-2023-RIA-CPL-2 (FAMES ID 101182279) projects were also acknowledged for their financial support.},
title = {On the Enhanced p‐Type Performance of Back‐Gated WS2 Devices},
doi = {10.1002/aelm.202500079},
author = {Márquez González, Carlos and Gity, Farzan and Galdón Gil, José Carlos and Martinez Garcia, Alberto and Salazar, Norberto and Ansari, Lida and Hazel, Neil and Donetti, Luca and Lorenzo Lazaro, Francisco and Caño-García, Manuel and Ortega López, Rubén and Navarro Moral, Carlos and Sampedro Matarín, Carlos and Hurley, Paul and Gámiz Pérez, Francisco Jesús},
}