@misc{10481/101734,
year = {2006},
month = {12},
url = {https://hdl.handle.net/10481/101734},
abstract = {We present the hardware implementation of a simple, fast technique for depth estimation based on phase measurement. This technique avoids the problem of phase warping and is much less susceptible to camera noise and distortion than standard block-matching stereo systems. The architecture exploits the parallel computing resources of FPGA devices to achieve a computation speed of 65 megapixels per second. For this purpose, we have designed a fine-grain pipeline structure that can be arranged with a customized frame-grabber module to process 52 frames per second at a resolution of 1280 x 960 pixels. We have measured the system's degradation due to bit quantization errors and compared its performance with other previous approaches. We have also used different Gabor-scale circuits, which can be selected by the user according to the application addressed and typical image structure in the target scenario.},
publisher = {IEEE},
keywords = {pipeline processing},
keywords = {scale space},
keywords = {stereo image processing},
keywords = {embedded and real-time systems},
title = {Real-Time System for High-Image Resolution Disparity Estimation},
doi = {10.1109/TIP.2006.884931},
author = {Díaz Alonso, Antonio Javier and Ros Vidal, Eduardo and Carrillo Sánchez, Richard Rafael and Prieto Espinosa, Alberto},
}