@misc{10481/101050,
year = {2022},
month = {5},
url = {https://hdl.handle.net/10481/101050},
abstract = {There is a growing interest in pushing computation to the edge, especially the problem-solving abilities of artificial neural networks (ANNs). This article presents a simplified method to obtain a ternary neural network based on the multilayer perceptron. The method is focused on resource-constrained devices, where memory, computing power, and battery are some of the most relevant constraints. A dynamic threshold is estimated to perform ternarization, and a new pruning technique is proposed to obtain a drastic reduction in the ANN’s size, with the corresponding decrease in resource utilization and power consumption of the resulting hardware. In addition, a support framework has been developed to automate hardware design exploration and generation from the network trained in software. Experimental results show that the proposed method and architecture, when implemented in a field-programmable gate array (FPGA), provide excellent figures in power (0.11–0.13 W) and efficiency (1225–1448 kfps/W) with respect to state of the art, being its efficiency double than the maximum one reported previously.},
organization = {Gobierno de España, ref. PGC2018-09733, NEUROWARE},
organization = {Horizonte 2020, ref. 876019},
organization = {Gobierno de España, ref. MIA.2021.M04.0008},
publisher = {IEEE},
title = {Power-efficient implementation of ternary neural networks in edge devices},
doi = {10.1109/JIOT.2022.3172843},
author = {Molina, Manuel and Méndez, Javier and Morales Santos, Diego Pedro and Castillo Morales, María Encarnación and López Vallejo, Marisa and Pegalajar Cuéllar, Manuel},
}