TY  - JOUR 
AU  - Navarro Moral, Carlos
AU  - Lacord, Joris
AU  - Parihar, Mukta Singh
AU  - Adamu-Lema, Fikru
AU  - Duan, Meng
AU  - Rodríguez Santiago, Noel
AU  - Cheng, Binjie
AU  - El Dirani, Hassam
AU  - Barbe, Jean-Charles
AU  - Fonteneau, Pascal
AU  - Bawedin, Maryline
AU  - Millar, Campbell
AU  - Galy, Philippe
AU  - Le Royer, Cyrille
AU  - Karg, Sigfried
AU  - Wells, Paul
AU  - Kim, Yong Tae
AU  - Asenov, Asen
AU  - Cristoloveanu, Sorin
AU  - Gámiz Pérez, Francisco Jesús
PY  - 2017
SN  - 0018-9383
UR  - http://hdl.handle.net/10481/47952
AB  - The Z2-FET operation as capacitorless DRAM is analyzed using advanced 2-D TCAD simulations for IoT applications. The simulated architecture is built based on actual 28-nm fully depleted silicon-on-insulator devices. It is found that the triggering...
LA  - eng
PB  - Institute of Electrical and Electronics Engineers (IEEE)
KW  - Semiconductor memories
KW  - Low-power
KW  - T-Dram
KW  - Capacitorless
KW  - Feedback effect
KW  - Fully depleted (FD)
KW  - Ground plane
KW  - Lifetime
KW  - Sharp switch
KW  - Silicon-on-insulator
KW  - Z2-FET
TI  - Extended analysis of the Z2-FET: Operation as capacitor-less eDRAM
DO  - 10.1109/TED.2017.2751141
ER  -