Extended analysis of the Z2-FET: Operation as capacitor-less eDRAM
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AutorNavarro Moral, Carlos; Lacord, Joris; Parihar, Mukta Singh; Adamu-Lema, Fikru; Duan, Meng; Rodríguez Santiago, Noel; Cheng, Binjie; El Dirani, Hassam; Barbe, Jean-Charles; Fonteneau, Pascal; Bawedin, Maryline; Millar, Campbell; Galy, Philippe; Le Royer, Cyrille; Karg, Sigfried; Wells, Paul; Kim, Yong Tae; Asenov, Asen; Cristoloveanu, Sorin; Gámiz Pérez, Francisco
Institute of Electrical and Electronics Engineers (IEEE)
Semiconductor memoriesLow-powerT-DramCapacitorlessFeedback effectFully depleted (FD)Ground planeLifetimeSharp switchSilicon-on-insulatorZ2-FET
Navarro Moral, C.; et al. Extended analysis of the Z2-FET: Operation as capacitor-less eDRAM. IEEE Transactions on Electron Devices, 64(11): 4486-4491 (2017). [http://hdl.handle.net/10481/47952]
The Z2-FET operation as capacitorless DRAM is analyzed using advanced 2-D TCAD simulations for IoT applications. The simulated architecture is built based on actual 28-nm fully depleted silicon-on-insulator devices. It is found that the triggering mechanism is dominated by the front-gate bias and the carrier’s diffusion length. As in other FB-DRAMs, the memory window is defined by the ON voltage shift with the stored body charge. However, the Z2-FET’s memory state is not exclusively defined by the inner charge but also by the reading conditions.